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Table 16.5. USART Parity Bits
STOP BITS [1:0]
00
01
10
11
Description
No parity bit (Default)
Reserved
Even parity
Odd parity
16.3.2.2 Clock Generation
The USART clock defines the transmission and reception data rate. When operating in asynchronous
mode, the baud rate (bit-rate) is given by Equation 16.1 (p. 181)
USART Baud Rate
br = f HFPERCLK /(oversample x (1 + USARTn_CLKDIV/256))
(16.1)
where f HFPERCLK is the peripheral clock (HFPERCLK USARTn ) frequency and oversample is the
oversampling rate as defined by OVS in USARTn_CTRL, see Table 16.6 (p. 181) .
Table 16.6. USART Oversampling
OVS [1:0]
00
01
10
11
oversample
16
8
6
4
The USART has a fractional clock divider to allow the USART clock to be controlled more accurately
than what is possible with a standard integral divider.
The clock divider used in the USART is a 15-bit value, with a 13-bit integral part and a 2-bit fractional
part. The fractional part is configured in the two LSBs of DIV in USART_CLKDIV. The lowest achievable
baud rate at 32 MHz is about 244 bauds/sec.
Fractional clock division is implemented by distributing the selected fraction over four baud periods. The
fractional part of the divider tells how many of these periods should be extended by one peripheral clock
cycle.
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated by using
Equation 16.2 (p. 181) :
USART Desired Baud Rate
USARTn_CLKDIV = 256 x (f HFPERCLK /(oversample x brdesired) - 1)
(16.2)
Table 16.7 (p. 182) shows a set of desired baud rates and how accurately the USART is able to
generate these baud rates when running at a 4 MHz peripheral clock, using 16x or 8x oversampling.
2011-04-12 - d0001_Rev1.10
181
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